1. Field
This disclosure relates generally to methods of making semiconductor structures, and more specifically, to methods useful in integrating fabrication of a split gate non-volatile memory cell with a logic device such as a transistor.
2. Related Art
The integration of non-volatile memories (NVMs) with logic transistors has always been a challenge due to the different requirements for the NVM transistors, which store charge, and the logic transistors which are commonly intended for high speed operation. The need for storing charge has been addressed mostly with the use of floating gates but also with nanocrystals or nitride. In any of these cases, the need for this unique layer makes integration of the NVM transistors and the logic transistors difficult. The particular type of charge storage layer can also have a large effect on the options that are available in achieving the integration. Logic devices that use high-k gate dielectric are also becoming more in demand to reduce leakage effects as gate dielectric thickness scales below 2 nanometers.
Even though logic devices with gate lengths of 28 nanometers are currently being produced, NVM that uses control gate over floating gate configurations has not proven to be reliable at such small scale. Thus, NVM with nanocrystals are a more viable option as gate lengths decrease. It is therefore desirable to provide integrated circuits with both logic devices and NVM that are formed using the same processing technology as gate lengths scale to 28 nanometers or less.